The present invention relates to a semiconductor device and a method for fabricating the same, more specifically a semiconductor device and a method for fabricating the same, the device having an insulation film formed on a surface of a semiconductor substrate, which is an inter-layer insulation film or others having tensile stress.
The method for fabricating a conventional semiconductor device having the multilayer interconnection structure formed on a semiconductor substrate will be explained with reference to FIGS. 14A-14C, 15A-15C and 16A-16B. FIGS. 14A-14C, 15A-15C and 16A-16B are sectional views of the semiconductor device having the multilayer interconnection structure in the steps of the method for fabricating the conventional semiconductor device having the multilayer interconnection structure.
First, a silicon oxide films 214a, 214b are formed respectively on the upper surface and the back surface of a silicon wafer 210 by, e.g., thermal oxidation.
Then, a silicon nitride films 216a, 216b are formed by, e.g., thermal CVD using a vertical furnace respectively on the silicon oxide films 214a, 214b formed respectively on the upper surface and the back surface of the silicon wafer 210 (FIG. 14A).
Then, a photoresist film 220 exposing regions for a device isolation film to be formed in and covering the rest region is formed on the silicon nitride film 216a on the upper surface of the silicon wafer 210 by photolithography (FIG. 14B).
Then, with the photoresist film 220 as a mask, the silicon nitride film 216a is etched. Thus, openings 222 are formed in the silicon nitride film 216a (FIG. 14C).
Next, with the photoresist film 220 and the silicon nitride film 216a as a mask, the silicon oxide film 214a and the silicon wafer 210 are respectively etched from the side of the upper surface of the silicon wafer 210. Thus, openings 224 are formed in the silicon oxide film 214a, and grooves 226 are formed in the surface of the silicon wafer 210.
After the grooves 226 are formed in the surface of the silicon wafer 210, the photoresist film 220 is removed by, e.g., ashing (FIG. 15A).
Next, a silicon oxide film 228 is formed on the entire upper surface of the silicon wafer 210 by, e.g., CVD (FIG. 15B).
Next, the silicon oxide film 228 is polished by, e.g., CMP until the upper surface of the silicon nitride film 216a is exposed to remove the silicon oxide film 228 on the silicon nitride film 216a. The silicon oxide film 228 is buried in the grooves 226 formed in the silicon wafer 210, the openings 224 formed in the silicon oxide film 214a and the openings 222 formed in the silicon nitride film 216a. Thus, the device isolation film of the silicon oxide film 228 is formed (FIG. 15C).
Then, the silicon nitride film 216a on the upper surface of the silicon wafer 210 is removed by wet etching. At this time, the silicon nitride film 216b on the back surface of the silicon wafer 210 is also etched off (FIG. 16A).
Next, the silicon oxide film 214a exposed on the upper surface of the silicon wafer 210 is removed by wet etching. At this time, the silicon oxide film 214b on the back surface of the silicon wafer 210 is also etched off (FIG. 16B).
On the upper surface of the silicon wafer 210 having the device region thus defined by the device isolation film 228, semiconductor devices, such as MOS transistors, etc., are formed.
On the upper surface of the silicon wafer 210 with semiconductor devices formed on, interconnection layers buried in inter-layer insulation films by single damascening, dual damascening or others are suitably repeatedly formed to thereby form a multilayer interconnection including a plurality of interconnection layers.
In forming a multilayer interconnection on the upper surface of a semiconductor substrate as of the above-described silicon wafer or others, when the inter-layer insulation films for the interconnection layers to be buried in are formed, the tensile stress of the inter-layer insulation films often causes the semiconductor substrate to warp convexly toward the back surface of the semiconductor substrate.
Recently, as semiconductor devices are required to be highly integrated, the layer number of interconnection layers forming multilayer interconnections formed on semiconductor substrates is increased. As semiconductor devices are required to be speedy, inter-layer insulation films with interconnection layers, etc. buried in are formed of low dielectric constant (low-k) insulation films.
Semiconductor substrates having such increased number of such low-k inter-layer insulation films formed on the surface are often caused to largely warp convexly toward the back surfaces due to the tensile stress of the inter-layer insulation films. Furthermore, diameters of semiconductor substrates used in fabricating semiconductor devices are increasing, which makes the warpage of semiconductor substrates tend to increase.
Here, as means for improving characteristics of the NMOS field effect transistors is known the means in which a silicon nitride film of, e.g., a 30-100 nm-thickness is formed between a semiconductor substrate and an upper layer of an interconnection layer or others formed on the upper surface thereof to thereby introduce strains due to a tensile stress of, e.g., 1-2 GPa of the silicon nitride film into the channel regions. However, the tensile stress of the insulation film formed between the semiconductor substrate and the upper layer, such as the interconnection layer or others formed on the upper surface thereof is a cause for the semiconductor substrate warping convexly toward the back surface thereof.
The warpage of the semiconductor substrate is a cause for the defective suction in the transfer system, in which semiconductor substrates are sucked by chucks, etc. to be transferred. Accordingly, such warpage of semiconductor substrate is required to be suppressed.
The background arts of the present invention are disclosed in e.g., Japanese published unexamined patent application No. Hei 09-64169 (1997) and Japanese published unexamined patent application No. Hei 10-32233 (1998).